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esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 1/45 revision history revision 0.1 (augut.30.1999) - original revision 0.2 (jun.04.2002) - add dc characteristics - add -5, -6 speed grade - delete ?8, -10, -12 speed grade revision 1.0 (oct.31.2002) - delete ?preliminary? revision 1.1 (mar.25.2003) - modify dc characteristics revision 1.2 (sep.02.2003) - delete -5 speed grace - speed distribution -6 and -7 revision 1.3 (aug.23.2004) - M12L128168A -6t 125mhz : cl = 3(p7) - correct polt2 clock suspend during read (p17) - correct polt5 : trdl(min) = 2clk (p20) - correct polt2 read interrupted by precharge - modify typing error of p18, p22, p23 revision 1.4 (oct.31.2002) - add pb-free to ordering information - modify p8 for bank precharge state to idle state revision 1.5 (apr.22.2005) - modify refresh spec revision 1.6 (jun.07.2005) - modify tref spec (15.6 s refresh interval 64ms 4k) - modify trfc ?7 spec (63ns 70ns)
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 2/45 sdram 2m x 16 bit x 4 banks synchronous dram features jedec standard 3.3v power supply lvttl compatible with multiplexed address four banks operation mrs cycle with address key programs - cas latency ( 2 & 3 ) - burst length ( 1, 2, 4, 8 & full page ) - burst type ( sequential & interleave ) all inputs are sampled at the positive going edge of the system clock burst read single write operation dqm for masking auto & self refresh 64ms refresh period (4k cycle) ordering information 54 pin tsop (type ii) (400mil x 875mil ) product no. max freq. package comments M12L128168A-6t 166mhz tsop ii pb M12L128168A-7t 143mhz tsop ii pb M12L128168A-6tg 166mhz tsop ii pb-free M12L128168A-7tg 143mhz tsop ii pb-free general description the M12L128168A is 134,217,728 bits synchronous high data ra te dynamic ram organized as 4 x 2,097,152 words by 16 bits. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle . range of operating frequencies, programmable burst length and programmable latencie s allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm we cas ras cs a 13 a 12 a 10 /ap a 0 a 1 a 2 a 3 v dd 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke nc a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 3/45 block diagram pin description pin name input function clk system clock active on the positive going edge to sample all inputs cs chip select disables or enables device operation by masking or enabling all inputs except clk , cke and l(u)dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior new command. disable input buffers for power down in standby. a0 ~ a11 address row / column address are multiplexed on the same pins. row address : ra0~ra11, column address : ca0~ca8 a12 , a13 bank select address selects bank to be activated during row address latch time. selects bank for read / write during column address latch time. ras row address strobe latches row addresses on the posit ive going edge of the clk with ras low. (enables row access & precharge.) cas column address strobe latches column address on the positive going edge of the clk with cas low. (enables column access.) we write enable enables write operation and row precharge. latches data in starting from cas , we active. l(u)dqm data input / output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when l(u)dqm active. dq0 ~ dq15 data input / output data input s / outputs are multiplexed on the same pins. v dd / v ss power supply / ground power and ground for the input buffers and the core logic. v ddq / v ssq data output power / ground isolated power supply and ground fo r the output buffers to provide improved noise immunity. n.c no connection this pin is recommended to be left no connection on the device. l(u)dqm dq mode register control logic column address buffer & counte r row a ddress buffer & refresh counter bank d row decoder bank a bank b bank c sense amplifier column decoder data control circuit latch circuit input & output buffer a ddress clock generator clk cke command decoder cs ras cas we
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 4/45 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 4.6 v storage temperature tstg -55 ~ +150 c power dissipation pd 1 w short circuit current i os 50 ma note : permanent device damage may occur if abso lute maximum rating are exceeded. functional operation should be restrict ed to recommended operating condition. exposure to higher than recommended voltage for exten ded periods of time could affect device reliability. dc operating condition recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c ) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i il -5 - 5 a 3 output leakage current i ol -5 - 5 a 4 note: 1. v ih (max) = 4.6v ac for pulse width 10ns acceptable. 2. v il(min) = -1.5v ac for pulse width 10ns acceptable. 3. any input 0v v in v dd + 0.3v, all other pins are not under test = 0v. 4. dout is disabled , 0v vout v dd . capacitance (v dd = 3.3v, t a = 25 c , f = 1mhz) parameter symbol min max unit input capacitance (a0 ~ a11, a13 ~ a12) c in1 2.5 4 pf input capacitance (clk, cke, cs , ras , cas , we & l(u)dqm) c in2 2.5 4 pf data input/output capacitance (dq0 ~ dq15) c out 2 6.5 pf
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 5/45 dc characteristics recommended operating condition unless otherwise noted t a = 0 to 70 c version parameter symbol test condition cas latency -6 -7 unit note operating current (one bank active) i cc1 burst length = 1, t rc t rc(min) , i ol = 0 ma 160 140 ma 1,2 i cc2p cke v il (max), tcc = t ck(min) 2 precharge standb y current in powe r -down mode i cc2ps cke & clk v il (max), t cc = 2 ma i cc2n cke v ih(min) , cs v ih(min) , t cc = t ck(min) input signals are changed one time during 2t ck 45 precharge standby current in non power-down mode i cc2ns cke v ih(min) , clk v il (max), tcc = input signals are stable 25 ma i cc3p cke v il (max), t cc = t ck(min) 6 active standby current in powe r -down mode i cc3ps cke & clk v il (max), t cc = 6 ma i cc3n cke v ih (min), cs v ih(min) , t cc = t ck(min) input signals are changed one time during 2t ck 55 ma active standby current in non power-down mode (one bank active) i cc3ns cke v ih(min) , clk v il (max), t cc = input signals are stable 35 ma operating current (burst mode) i cc4 i ol = 0 ma, page burst, 2 banks activated 210 180 ma 1,2 refresh current i cc5 t rc t rc(min) 210 180 ma self refresh current i cc6 cke 0.2v 2 ma note : 1. measured with outputs open. 2. input signals are changed one time during 2 clks.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 6/45 ac operating test conditions (v dd = 3.3v 0.3v t a = 0 to 70 c ) parameter value unit input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall-time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 (fig. 1) dc output load circuit (fig. 2) ac output load circuit operating ac parameter (ac operating conditions unless otherwise noted) version parameter symbol -6 -7 unit note row active to row active delay t rrd(min) 12 14 ns 1 ras to cas delay t rcd(min) 18 20 ns 1 row precharge time t rp(min) 18 20 ns 1 t ras(min) 42 42 ns 1 row active time t ras(max) 100 us @ operating t rc(min) 60 63 ns 1 row cycle time @ auto refresh t rfc(min) 60 70 ns 1,5 last data in to col. address delay t cdl(min) 1 t ck 2 last data in to row precharge t rdl(min) 2 t ck 2 last data in to burst stop t bdl(min) 1 t ck 2 refresh period (4,096 rows) t bef(max) 64 ms 6 output 870 v oh (dc) =2.4v , i oh = -2 ma v ol (dc) =0.4v , i ol = 2 ma output 50pf z0 =50 50pf 50 vtt = 1.4v 3.3v 1200 ? ? ? ?
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 7/45 version parameter symbol -6 -7 unit note col. address to col. address delay t ccd(min) 1 t ck 3 cas latency = 3 2 number of valid output data cas latency = 2 1 ea 4 note : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interr upt, auto precharge and read burst stop. 5. a new command may be given t rfc after self refresh exit. 6. a maximum of eight consecutiv e auto refresh commands (with t rfcmin ) can be posted to any given sdram, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8x15.6 s.) ac characteristics (ac operating condition unless otherwise noted) -6 -7 parameter symbol min max min max unit note cas latency = 3 6 7 clk cycle time cas latency = 2 t cc 10 1000 10 1000 ns 1 cas latency = 3 - 5.4 - 5.4 clk to valid output delay cas latency = 2 t sac - 6 - 6 ns 1,2 cas latency = 3 2.5 - 2.5 - output data hold time cas latency = 2 t oh 2.5 - 2.5 - ns 2 clk high pulsh width t ch 2.5 - 2.5 - ns 3 clk low pulsh width t cl 2.5 - 2.5 - ns 3 input setup time t ss 1.5 - 1.5 - ns 3 input hold time t sh 1 - 1 - ns 3 clk to output in low-z t slz 1 - 1 - ns 2 cas latency = 3 - 5.4 - 5. 4 clk to output in hi-z cas latency = 2 t shz - 6 - 6 ns - note : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns . (tr/2 - 0.5) ns should be considered. 3. assumed input rise and fall time (tr & tf) =1ns. if tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 ? 1] ns should be added to the parameter.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 8/45 frequency vs. ac parameter relationship table M12L128168A-6t (unit: number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 60 42 18 12 18 6 6 12 166 mhz(6.0ns ) 3 10 7 3 2 3 1 1 2 143 mhz(7.0ns ) 3 9 6 3 2 3 1 1 2 125 mhz(8.0ns ) 3 8 6 3 2 3 1 1 2 100 mhz(10.0ns ) 2 6 5 2 2 2 1 1 2 83 mhz(12.0ns ) 2 5 4 2 1 2 1 1 1 M12L128168A-7t (unit: number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 63 42 20 14 20 7 7 14 143 mhz(7.0ns ) 3 9 6 3 2 3 1 1 2 125 mhz(8.0ns ) 3 8 6 3 2 3 1 1 2 100 mhz(10.0ns ) 2 7 5 2 2 2 1 1 2 83 mhz(12.0ns ) 2 6 4 2 2 2 1 1 2 75 mhz(13.0ns ) 2 5 4 2 2 2 1 1 2 M12L128168A-6tg (unit: number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 60 42 18 12 18 6 6 12 166 mhz(6.0ns ) 3 10 7 3 2 3 1 1 2 143 mhz(7.0ns ) 3 9 6 3 2 3 1 1 2 125 mhz(8.0ns ) 3 8 6 3 2 3 1 1 2 100 mhz(10.0ns ) 2 6 5 2 2 2 1 1 2 83 mhz(12.0ns ) 2 5 4 2 1 2 1 1 1 M12L128168A-7tg (unit: number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl frequency cas latency 63 42 20 14 20 7 7 14 143 mhz(7.0ns ) 3 9 6 3 2 3 1 1 2 125 mhz(8.0ns ) 3 8 6 3 2 3 1 1 2 100 mhz(10.0ns ) 2 7 5 2 2 2 1 1 2 83 mhz(12.0ns ) 2 6 4 2 2 2 1 1 2 75 mhz(13.0ns ) 2 5 4 2 2 2 1 1 2
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 9/45 simplified truth table command cken-1 cken cs ras cas we dqm a13 a12 a10/ap a11 a9~a0 note register mode register se t h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h x 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge enable h x l h l h x v h column address (a0~a8) 4,5 auto precharge disable l 4 write & column address auto precharge enable h x l h l l x v h column address (a0~a8) 4,5 burst stop h x l h h l x x 6 bank selection v l precharge all banks h x l l h l x x h x h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dqm h x v x 7 h x x x no operating command h x l h h h x x (v = valid , x = don?t care. h = logic high , l = logic low ) note : 1.op code : operating code a0~a11 & a13~a12 : program keys. (@ mrs) 2.mrs can be issued only at a ll banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3.auto refresh functions are as same as cbr refresh of dram. the automatical precharge wi thout row precharge of command is meant by ?auto?. auto/self refresh can be issued only at all banks idle state. 4.a13~a12 : bank select addresses. if a13 and a12 are ?low? at read ,write , row active and precharge ,bank a is selected. if a13 is ?low? and a12 is ?high? at read ,write , row active and precharge ,bank b is selected. if a13 is ?high? and a12 is ?low? at read ,write , row active and precharge ,bank c is selected. if a13 and a12 are ?high? at read ,write , row active and precharge ,bank d is selected if a10/ap is ?high? at row precharge , a13 an d a12 is ignored and all banks are selected. 5.during burst read or write with auto precha rge. new read/write command can not be issued. another bank read/write command ca n be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6.burst stop command is valid at every burst length. 7.dqm sampled at positive goi ng edge of a clk and masks the dat a-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after.(read dqm latency is 2)
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 10/45 mode register field table to program modes register programmed with mrs address a13~a12 a11~a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu rfu w.b.l. tm cas latency bt burst length test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt = 0 bt = 1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 reserved 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 0 1 0 4 4 1 1 reserved 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page reserved full page length : 512 power up sequence 1.apply power and start clock, attempt to maintain cke = ?h?, dqm = ?h? and the othe r pin are nop condition at the inputs. 2. maintain stable power , stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue mode register set command to initialize the mode register. cf.) sequence of 4 & 5 is regardless of the order. the device is now ready for normal operation. note : 1. rfu(reserved for future us e) should stay ?0? during mrs cycle. 2. if a9 is high during mrs cycle, ? burst read single write? function will be enabled.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 11/45 burst sequence (burst length = 4) initial adrress a1 a0 sequential interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence (burst length = 8) initial a2 a1 a0 sequential interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 12/45 device operations clock (clk) the clock input is used as the reference for all sdram operations. all operations are sy nchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and icc specifications. clock enable(cke) the clock enable (cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of out put and burst address is frozen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the po wer down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least ?1clk + t ss ? before the high going edge of the cl ock, then the sdram becomes active from the same clock edge accepting all the input commands. bank addresses (a13~a12) this sdram is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. the a13~a12 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the banks addressed a13~a12 are latched at bank active, read, write, mode register set and precharge operations. address inputs (a0~a11) the 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (a0~a11). the 12 row addresses are latched along with ras and a13~a12 during bank active command. the 9 bit column addresses are latched along with cas , we and a13~a12 during read or with command. nop and device deselect when ras , cas and we are high , the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. the device des elect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we and all the address inputs are ignored. power-up 1.apply power and start clock, attempt to maintain cke = ?h?, dqm = ?h? and the other pins are nop condition at the inputs. 2.maintain stable power, stable clock and nop input condition for minimum of 200us. 3.issue precharge commands for both banks of the devices. 4.issue 2 or more auto-refresh commands. 5.issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 is regardless of the order. the device is now ready for normal operation. mode register set (mrs) the mode register stores t he data for controlling the various operating modes of sdram. it programs the cas latency, burst type, burst length, test mode and various vendor specific options to ma ke sdram useful for variety of different applications. t he default value of the mode register is not defin ed, therefore the m ode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas and we (the sdram should be in active mode with cke already high prior to writing the mode register). the state of address pins a0~a11 and a13~a12 in the same cycle as cs , ras , cas and we going low is the data written in the mode register. two clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields into depending on functionality. the burst length field uses a0~a2, burst type uses a3, cas latency (read latency from column address) use a4~a6, vendor specific options or test mode use a7~a8, a10/ap~a11 and a13~a 12. the write burst length is programmed using a9. a7~a8, a10/ap~a11 and a13~a12 must be set to low for normal sdram operation. refer to the table for specific codes for various burst length, burst type and cas latencies. bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank address, a row access is initiated. the read or write operation can occur after a time delay of t rcd(min) from the time of bank activation. t rcd is the internal timing paramete r of sdram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 13/45 device operations (continued) dividing t rcd(min) with cycle time of the clock and then rounding of the result to the next higher integer. the sdram has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, t herefore it restricts the activation of four banks simultaneously. also the noise generated during sensing of each bank of sdram is high requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd(min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras(min) . every sdram bank activate command must satisfy t ras(min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and ras with we being high on the positive edge of the clock. the bank must be active for at least t rcd(min) before the burst read command is issued. the first output appears in cas latency number of clock cycles after the issue of burst read command. the burst length, bur st sequence and latency from the burst read command is dete rmined by the mode register which is already programmed. t he burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in t he mode register. the output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. the burst read can be terminated by i ssuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. burst write the burst write command is similar to burst read command and is used to write data into the sdram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a writ e burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write co mmand. the input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. the writing can be complete by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. the write burst can also be terminated by using dqm for blocking data and precharge the bank t rdl after the last data input to be written into the active ro w. see dqm operation also. dqm operation the dqm is used mask input and output operations. it works similar to oe during operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during burst interrupts of write with read or precharge in the sdram. due to asynchrono us nature of the internal write, the dqm operation is crit ical to avoid unwanted or incomplete writes when the complete burst write is required. please refer to dqm timing diagram also. precharge the precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and cs , ras , we and a10/ap with valid a13~a12 of the bank to be procharged. the precharge command can be asserted anytime after t ras(min) is satisfy from the bank active command in the desired bank. t rp is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t rp with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank has to be precharge with t ras (max) from the bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power-down, auto refresh, self refresh and mode register set etc. is possible only when all banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras(min) and ?t rp ? for the programmed burst length and cas latency. the auto precharge command is issued at the same time as bur st write by asserting high on a10/ap, the bank is precharge command is asserted. once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. four banks precharge four banks can be precharged at the same time by using precharge all command. asserting low on cs , ras , and we with high on a10/ap after all banks have satisfied t ras(min) requirement, performs precharge on all banks. at the end of t rp after performing precharge all, all banks are in idle state.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 14/45 device operations (continued) auto refresh the storage cells of sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refr esh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to complete the auto refresh operation is specified by t rfc(min) . the minimum number of clock cycles required can be calculated by driving t rfc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop?s until the auto refresh oper ation is completed. the auto refresh is the preferred refresh mode when the sdram is being used for normal data transactions. the auto refresh cycle can be performed once in 15.6us. self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power oper ation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing is internally generated to reduce power consumption. the self refresh mode is enter ed from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low matters, all the other inputs including clock are ignored to remain in the refresh. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop?s for a minimum time of t rfc before the sdram reaches idle state to begin normal operation. it is recommended to use burst 4096 auto refresh cycles immediately before and after self refresh.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 15/45 commands mode register set command ( cs , ras , cas , we = low) the M12L128168A has a mode register that defines how the device operates. in this command, a0 through a13 are the data input pins. after power on, the mode register set command must be exec uted to initialize the device. the mode register can be set only when all banks are in idle state. during 2clk following this command, the M12L128168A cannot accept any other commands. activate command ( cs , ras = low, cas , we = high) the M12L128168A has four banks, each with 4,096 rows. this command activates the bank selected by a12 and a13 (bs) and a row address selected by a0 through a11. this command corresponds to a conventional dram?s ras falling. precharge command ( cs , ras , we = low, cas = high ) this command begins precharge operation of the bank selected by a12 and a13 (bs). when a10 is high, all banks are pr echarged, regardless of a12 and a13. when a10 is low, only the bank selected by a12 and a13 is precharged. after this command, the M12L128168A can?t accept the activate command to the precharging bank during t rp (precharge to acti vate command period). this command corresponds to a conventional dram?s ras rising. clk clk cke cke cs cs ras ras we we a12, a13 a12, a13 (bank select) a10 a10 add add cas cas h h row row fig. 1 mode register set command fig. 2 row address strobe and bank active command clk cke cs ras we a12, a13 (bank select) a10 (precharge select) add cas h fig. 3 precharge command
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 16/45 write command ( cs , cas , we = low, ras = high) if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst can be input with this command with subsequent data on following clocks. read command ( cs , cas = low, ras , we = high) read data is available after cas latency requirements have been met. this command sets the burst start address given by the column address. cbr (auto) refresh command ( cs , ras , cas = low, we , cke = high) this command is a request to begin the cbr refresh operation. the refresh address is generated internally. before executing cbr refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to re fresh or activate command), the M12L128168A cannot acc ept any other command. clk clk cke cke cs cs ras ras we we a12, a13 (bank select) a12, a13 (bank select) a10 a10 add add cas cas h h col. fig. 4 column address and write command fig. 5 column address and read command clk cke cs ras we a12, a13 (bank select) a10 add cas h fig. 6 auto refresh command col.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 17/45 self refresh entry command ( cs , ras , cas , cke = low , we = high) after the command execution, self re fresh operation continues while cke remains low. when cke goes to high, the M12L128168A exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. burst stop command ( cs , we = low, ras , cas = high) this command terminates the current burst operation. burst stop is valid at every burst length. no operation ( cs = low , ras , cas , we = high) this command is not a execution command. no operations begin or terminate by this command. clk cke cs ras we a12, a13 (bank select) a10 add cas clk cke cs ras we a12, a13 (bank select) a10 add cas h fig. 7 self refresh entry command fig. 8 burst stop command clk cke cs ras we a12, a13 (bank select) a10 add cas h fig. 9 no operation
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 18/45 basic feature and function descriptions 1. clock suspend 2. dqm operation *note : 1. cke to clk disable/enable = 1clk. 2. dqm masks data out hi-z after 2clks which should masked by cke ?l?. 3. dqm masks both data-in and data-out. clk cmd dqm dq(cl2) dq(cl3) rd q0 q2 q3 q1 q2 q3 d0 d1 d3 d1 d3 d0 wr masked by dqm masked by dqm clk cmd dqm dq(cl2) dq(cl3) cke rd q0 q2 q4 hi-z hi-z hi-z q6 q7 q8 q5 q6 q7 q1 q3 hi-z hi-z hi-z hi-z hi-z 1)write mask (bl=4) 2)read mask (bl=4) dqm to data-in mask=0 dqm to data-out mask=2 3)dqm with clcok suspended (full page read) *note2 internal clk clk cmd cke internal clk dq(cl2) dq(cl3) rd q2 q0 q1 q3 q2 q0 q1 q3 d0 d1 d2 d3 d1 d2 d3 d0 wr masked by cke 1) clock suspended during write (bl=4) 2) clock suspended during read (bl=4) not written suspended dout
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 19/45 3. cas interrupt (i) clk cmd add dq(cl2) dq(cl3) rd qb0 qb2 qa0 clk cmd add dq wr da0 db0 db1 rd a b qb1 qb3 qb0 qb2 qa0 qb3 qb1 t ccd *not e 2 wr t cc d *no te 2 a b t cdl *note 3 wr rd t ccd *note 2 a b da0 db0 db1 t cdl *note 3 da0 db0 db1 dq(cl3) dq (c l2) 1)read interrupted by read (bl=4) 2) wr i te i n ter ru pte d b y w ri te (b l= 2) 3 )w ri te in ter rup ted by r ead (b l=2 ) *no t e1 *note : 1. by ?interrupt? is meant to stop burst read/write by external before the end of burst. by ? cas interrupt ?, to stop burst read/write by cas access ; read and write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk)
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 20/45 4. cas interrupt (ii) : read interrupted by write & dqm clk i)cmd dqm dq d1 d3 d0 d2 wr ii)cmd dqm dq iii)cmd dqm dq iv)cmd dqm dq d1 d3 d0 d2 rd wr rd wr d1 d3 d0 d2 d1 d3 d0 d2 rd wr hi-z q0 *note1 hi-z hi-z hi-z (a)cl=2,bl=4 rd
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 21/45 *note : 1. to prevent bus cont ention, there should be at least one gap between data in and data out. 5. write interrupted by precharge & dqm *note : 1. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. 2. to inhibit invalid wr ite, dqm should be issued. 3. this precharge command and burst writ e command should be of the same bank, ot herwise it is not precharge interrupt but only another bank prechar ge of four banks operation. clk i)cmd ii)cmd iii)cmd iv)cmd dqm dqm dqm dqm dq dq dq dq d1 d3 d1 d0 d2 d3 d0 d2 wr (b)cl=3,bl=4 rd wr rd wr d1 d3 d0 d2 d1 d3 d0 d2 rd wr hi-z d1 d3 d0 d2 q0 *note1 v)cmd dqm dq rd wr hi-z rd clk cmd dqm dq d1 wr *n ote 3 * masked by dqm d 3 t rdl(min) pre note2 d 0 d2
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 22/45 6. precharge . 7. auto precharge *note : 1. t rdl : last data in to row precharge delay. 2. number of valid output data after row pr echarge : 1,2 for cas latency = 2,3 respectively. 3. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas in terrupt of the same/another bank is illegal. clk cmd dq d0 d1 d2 d3 wr t rdl *note1 clk cmd cmd dq(cl2) q0 q1 q2 q3 rd pre dq(cl3) q0 q1 q2 q3 pre 1)no r mal w r ite (bl=4) 2)normal read (bl=4) cl=2 pre cl=3 *note2 *note2 clk cmd dq d0 d1 d2 d3 wr clk cmd dq(cl2) d0 d1 d2 d3 rd dq(cl3) *note3 auto precharge starts d0 d1 d2 d3 *note3 auto precharge starts 1 ) no r mal w r ite ( bl=4 ) 2 ) no r mal read ( bl=4 ) t rdl (min)
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 23/45 8. burst stop & interrupted by precharge 9. mrs *note: 1. t bdl : 1 clk ; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 2. number of valid output data after burst stop : 1,2 for cas latency = 2,3 respectiviely. 3. write burst is terminated. t bdl determinates the last data write. 4. dqm asserted to prevent corruption of locations d2 and d3. 5. precharge can be issued here or earlier (satisfying t ras min delay) with dqm. 6. pre : all banks precharge, if necessary. mrs can be issued only at all banks precharge state. clk cmd pre *note4 mrs act t rp 2clk 1)mode register set clk cmd dq(cl2) dq(cl3) clk cmd dqm dq d0 d1 d2 d3 wr stop *note1 q0 q1 q0 q1 rd stop *note2 1)wri t eburs t s t o p (bl=8) 2)read burst stop (bl=4) d5 d4 clk cmd dq(cl3) clk cmd dqm dq d0 d1 mask mask wr q0 q1 rd pre 1)wri t ein t erru p t ed b y p recharge (bl=4) 2)read interrupted by precharge (bl=4) *note2 pre *note4 *note3 dq(cl2) *note5 q2 q1 q2 q3 q0 t rdl t bdl q3
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 24/45 10. clock suspend exit & power down exit 11. auto refresh & self refresh *note : 1. active power down : one or more banks active state. 2. precharge power down : all banks precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are required after auto refresh command. during t rfc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, all banks must be idle state. 5. mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh entry, refresh interval and refresh operation are performed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh entry, all inputs expect cke will be don?t cared, and outputs will be in hi-z state. for the time interval of t rfc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh (4096 cycles) is recommended. clk cke internal clk cmd rd t ss *note1 clk cke internal clk cmd act t ss *note2 nop 1)clock suspend(= a ctive powe r down)exit 2)powe r down (=p r echa r ge powe r down) clk cmd pre ar cke cmd t rp t rfc *note5 *note4 clk cmd pre sr cke cmd t rp t rfc *note4 1)auto refresh & self refresh 2)self refresh *no t e3 *note6
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 25/45 12. about burst type control sequential counting at mrs a3 = ?0?. see the burst sequence table. (bl = 4,8) bl = 1, 2, 4, 8 and full page. basic mode interleave counting at mrs a3 = ?1?. see the burst sequence table. (bl = 4,8) bl = 4, 8 at bl =1, 2 interleave counting = sequential counting random mode random column access tccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. 13. about burst length control 1 at mrs a210 = ?000? at auto precharge . t ras should not be violated. 2 at mrs a210 = ?001? at auto precharge . t ras should not be violated. 4 at mrs a210 = ?010? 8 at mrs a210 = ?011? basic mode full page at mrs a210 = ?111? at the end of the burst length , burst is warp-around. special mode brsw at mrs a9 = ?1? read burst = 1,2,4,8, full page write burst =1 at auto precharge of write, t ras should not be violated. random mode burst stop tbdl = 1, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. using burst stop command, any burst length control is possible. ras interrupt (interrupted by precharge) before the end of burst. row precharge comm and of the same bank stops read /write burst with auto precharge. t rdl = 1 with dqm , valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. during read/write burst with auto precharge, ras interrupt can not be issued. interrupt mode cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst. during read/write burst with auto precharge, cas interrupt can not be issued.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 26/45 function turth table (table 1) current state cs ras cas we ba addr action note h x x x x x nop l h h h x x nop l h h l x x illegal 2 idle l h l x ba ca, a10/ap illegal 2 l l h h ba ra row (&bank) active ; latch ra l l h l ba a10/ap nop 4 l l l h x x auto refresh or self refresh 5 l l l l op code op code mode register access 5 h x x x x x nop l h h h x x nop l h h l x x illegal 2 row l h l h ba ca, a10/ap begin read ; latch ca ; determine ap active l h l l ba ca, a10/ap begin write ; latch ca ; determine ap l l h h ba ra illegal 2 l l h l ba a10/ap precharge l l l x x x illegal h x x x x x nop (continue burst to end row active) l h h h x x nop (continue burst to end row active) l h h l x x term burst row active read l h l h ba ca, a10/ap term burst, new read, determine ap l h l l ba ca, a10/ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a10/ap term burst, precharge timing for reads l l l x x x illegal h x x x x x nop (continue burst to end row active) l h h h x x nop (continue burst to end row active) l h h l x x term burst row active write l h l h ba ca, a10/ap term burst, new read, determine ap 3 l h l l ba ca, a10/ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a10/ap term burst, precharge timing for writes 3 l l l x x x illegal h x x x x x nop (continue burst to end row active) read with l h h h x x nop (continue burst to end row active) auto l h h l x x illegal precharge l h l x ba ca, a10/ap illegal l l h x ba ra, ra10 illegal 2 l l l x x x illegal h x x x x x nop (continue burst to end row active) write with l h h h x x nop (continue burst to end row active) auto l h h l x x illegal precharge l h l x ba ca, a10/ap illegal l l h x ba ra, ra10 illegal 2 l l l x x x illegal
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 27/45 current state cs ras cas we ba addr action note h x x x x x nop idle after trp read with l h h h x x nop idle after trp auto l h h l x x illegal 2 precharge l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10/ap nop idle after trpl 4 l l l x x x illegal h x x x x x nop row active after trcd l h h h x x nop row active after trcd row l h h l x x illegal 2 activating l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10/ap illegal 2 l l l x x x illegal h x x x x x nop idle after trfc l h h x x x nop idle after trfc refreshing l h l x x x illegal l l h x x x illegal l l l x x x illegal h x x x x x nop idle after 2clocks mode l h h h x x nop idle after 2clocks register l h h l x x illegal accessing l h l x x x illegal l l x x x x illegal abbreviations : ra = row address ba = bank address nop = no operation command ca = col umn address ap = auto precharge *note : 1. all entries assume the cke was active (high) during the precharge clock and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of the bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharge or in idle state. ma y precharge bank indicated by ba (and a10/ap). 5. illegal if any bank is not idle.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 28/45 function truth table (table2) current state cke ( n-1 ) cke n cs ras cas we addr action note h x x x x x x invalid l h h x x x x exit self refresh idle after trfc (abi) 6 self l h l h h h x exit self refresh idle after trfc (abi) 6 refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self refresh) h x x x x x x invalid all l h h x x x x exit self refresh abi 7 banks l h l h h h x exit self refresh abi 7 precharge l h l h h l x illegal power l h l h l x x illegal down l h l l x x x illegal l l x x x x x nop (maintain low power mode) h h x x x x x refer to table1 h l h x x x x enter power down 8 h l l h h h x enter power down 8 h l l h h l x illegal all h l l h l x x illegal banks h l l l h h ra row (& bank) active idle h l l l h h x nop h l l l l l x enter self refresh 8 h l l l l l op code mode register access l l x x x x x nop any state h h x x x x x refer to operations in table 1 other than h l x x x x x begin clock suspend next cycle 9 listed l h x x x x x exit clock suspend next cycle 9 above l l x x x x x maintain clock suspend abbreviations : abi = all banks idle, ra = row address *note : 6.cke low to high transition is asynchronous. 7.cke low to high transition is asynchronous if restart internal clock. a minimum setup time 1clk + t ss must be satisfy before any command other than exit. 8.power down and self refresh can be entered only from the all banks idle state. 9.must be a legal command.
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 29/45 single bit read-write-read cycle(same page) @ cas latency = 3,burst length = 1 : d o n ' t c a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13,a12 t ch t cl t cc t ras t rc t s h t ss t rcd t sh t ss t sh t ss row active read write read row active precharge *note2 t rp t ss ra t sh rb t sh t ss t sh t ss t ss t oh t slz t sac *note3 *note4 *note2,3 *note2,3 *note2,3 bs bs bs cb cc *note3 db qa *note3 *note4 t sh bs bs bs *note1 high t ccd ra *note2 ca qc rb
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 30/45 note : 1. all input expect cke & dqm can be don?t care when cs is high at the clk high going edge. 2. bank active @ read/write are controlled by a13~a12. a13 a12 active & read/write 0 0 bank a 0 1 bank b 1 0 bank c 1 1 bank d 3. enable and disable auto precharge function are controlled by a10/ap in read/write command a10/ap a13 a12 operating 0 0 disable auto precharge, leave a bank active at end of burst. 0 1 disable auto precharge, leave b bank active at end of burst. 1 0 disable auto precharge, leave c bank active at end of burst. 0 1 1 disable auto precharge, leave d bank active at end of burst. 0 0 enable auto precharge , pr echarge bank a at end of burst. 0 1 enable auto precharge , pr echarge bank b at end of burst. 1 0 enable auto precharge , precharge bank c at end of burst. 1 1 1 enable auto precharge , precharge bank d at end of burst. 4. a10/ap and a13~a12 control bank precharge when precharge is asserted. a10/ap a13 a12 precharge 0 0 0 bank a 0 0 1 bank b 0 1 0 bank c 0 1 1 bank d 1 x x all banks
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 31/45 power up sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap t rp key raa a13 a12 raa high-z precharge (all banks) auto refresh auto refresh mode register set row active (a-bank) : don't care t rfc t rfc high level is necessary high level is necessary
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 32/45 read & write cycle at same bank @ burst length = 4 *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency-1] number of valid output data is available after row precharge. last valid output will be hi-z (t shz ) after the clock. 3. output will be hi-z after the end of burst. (1,2,4,8 & full page bit burst) t rcd t rc high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap a12 a13 cl=2 cl=3 ` t rdl db0 db3 db1 db2 ra ca rb cb ra rb t oh t oh t sac t sac t shz t shz write (a-bank) read row active precharge (a-bank) (a-bank) (a-bank) precharge (a-bank) row active (a-bank) *note2 *note3 *note3 : don't care *note1 qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 t rdl db0 db3 db1 db2
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 33/45 page read & write cycle at same bank @ burst length = 4 note : 1. to write data before burst read ends. dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input , t rdl before row precharge , will be written. 3. dqm should mask invalid input data on precharge command cy cle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13 a12 cl =2 cl =3 *note3 row active ( a - bank ) read ( a - bank ) read ( a - bank ) write ( a - bank ) write ( a - bank ) precharge (a - bank) : d o n ' t c a r e qa0 qa1 qb0 qb1 dd0 dd1 t cdl dc1 dc0 qa1 qb0 qb1 qb2 dc1 dd0 dd1 dc0 qa0 ra *note2 cc cd ra ca cb *note1 high t rcd t rdl
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 34/45 page read cycle at different bank @ burst length = 4 note: 1. cs can be don?t cared when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. r o w a c t i v e ( a - b a n k ) r o w a c t i v e ( b - b a n k ) r e a d ( a - b a n k ) r o w a c t i v e ( c - b a n k ) r e a d ( b - b a n k ) p r e c h a r g e ( a - b a n k ) r o w a c t i v e ( d - b a n k ) r e a d ( c - b a n k ) p r e c h a r g e ( b - b a n k ) r e a d ( d - b a n k ) p r e c h a r g e ( c - b a n k ) p r e c h a r g e ( d - b a n k ) : d o n ' t c a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we cl=2 dqm a10/ap a13 a12 cl=3 rbb caa rcc cbb rdd ccc cdd *note1 *note2 raa rdd qbb0 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qaa1 qaa0 qaa2 qbb1 qaa0 qaa1 qaa2 qbb0 qcc1 qcc2 qdd0 qdd2 qdd1 qbb1 qcc0 qbb2 raa rbb rcc high dq qdd2
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 35/45 page write cycle at different bank @ burst length = 4 *note : 1. to interrupt burst write by row precharge , dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge , both the write and the precharge banks must be the same. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 7 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13 a12 : don't care *note1 raa rbb caa cbb rdd ccc rcc cdd *note2 daa1 daa0 dbb0 dbb1 dbb3 ddd0 ddd1 daa2 dbb2 dcc0 dcc1 raa rbb rcc rdd daa3 cdd2 t cdl r o w a c t i v e ( a - bank ) r o w a c t i v e ( b - b a n k ) w r i t e ( a - b a n k ) w r i t e ( b - b a n k ) r o w a c t i v e ( c - b a n k ) w r i t e ( c - b a n k ) p r e c h a r g e ( a l l b a n k s ) r o w a c t i v e ( d - b a n k ) w r i t e ( d - b a n k ) high t rdl
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 36/45 read & write cycle at different bank @ burst length = 4 *note : 1. t cdl should be met to complete write. clock cke cs ras cas addr we dq dqm a10/ap a13 a12 cl =2 cl =3 row active (a-bank) read (b-bank) : d o n ' t c a r e qaa1 qaa2 qaa3 ddb1 ddb2 ddd3 ddb0 qaa0 raa cbc raa caa qaa1 qaa2 qaa3 ddb1 ddb2 ddd3 ddb0 qaa0 write (d-bank) high rdb cdb rbc rbb rac qbc0 qbc1 qbc2 qbc0 qbc1 read (a-bank) row active (d-bank) precharge (a-bank) row active (b-bank) t cdl *note1 19 210 3 4 5 6 7 8 11 12 13 14 17 15 18 16 19 0
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 37/45 read & write cycle with auto precharge @ burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13 a12 cl =2 cl =3 row active ( a - bank ) row active ( d - bank ) auto precharge start point read with auto precharge ( a - bank ) auto precharge start point (d-bank) : d o n ' t c a r e qaa1 qaa2 qaa3 ddb1 ddb2 ddd3 ddb0 qaa0 ra cb ra ca rb rb qaa1 qaa2 qaa3 ddb1 ddb2 ddd3 ddb0 qaa0 write with auto precharge (d-bank) high
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 38/45 clock suspension & dqm operation cycle @ cas letency = 2 , burst length = 4 *note : 1. dqm is needed to prevent bus contention clock cke cs ras cas addr we dq dqm a10/ap a13 a12 ra ca cb cc ra qa0 qa1 qa2 qa3 t shz qb1 qb0 t shz dc0 dc2 *note1 row active read clock suspension read read dqm write write dqm clock suspension write dqm :don't care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 39/45 read interrupted by precharge command & read burst stop cycle @ burst length = full page *note : 1. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycles?. 2. burst stop is valid at every burst length. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 7 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13 a12 raa caa cab raa qaa0 qaa1 qab1 qab0 qab2 *note1 row active (a-bank) read (a-bank) burst stop read (a-bank) :don't care high cl=2 cl=3 qaa2 qaa3 qaa4 qab3 qab4 qab5 qaa0 qaa1 qab1 qab0 qab2 qaa2 qaa3 qaa4 qab3 qab4 qab5 1 2 precharge (a-bank) 1 2
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 40/45 write interrupted by precharge command & write burst stop cycle @ burst length = full page *note : 1. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defin ed by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycl e when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 2. burst stop is valid at every burst length. clock cke cs ras cas addr we dq dqm a10/ap a13 a12 raa caa cab raa daa0 daa1 dab1 dab0 dab2 row active (a-bank) write (a-bank) burst stop write (a-bank) :don't care high daa2 daa3 daa4 dab3 dab4 dab5 precharge (a-bank) t bdl t rdl *note1 19 210 34 5 678 11 12 13 14 17 15 18 16 19 0
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 41/45 active/precharge power down mode @ cas latency = 2, burst length = 4 *note: 1. both banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + t ss prior to row active command. 3. can not violate minimum refresh specification. clock cke cs ras cas addr we dq dqm a10/ap a12 active power-down exit precharge : don't care *note3 *note2 *note1 t ss t ss t ss ra ra qa0 qa1 qa2 t shz precharge power-down entry precharge power-down exit row active active power-down entry read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ca a13
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 42/45 self refresh entry & exit cycle *note : to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rfc is required after cke going high to complete self refresh exit. 7. 4k cycle of burst auto refresh is required before self refres h entry and after self refresh exit if the system uses burst refresh. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap a13,a12 self refresh entry auto refresh : don't care *note2 *note1 t ss *note3 *note4 t rfc min *note6 self refresh exit hi-z hi-z *note5 *note7
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 43/45 mode register set cycle auto refresh cycle all banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle *note : 1. cs , ras , cas , & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. clock cke cs ras cas addr we dq dqm :don't care high 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 high key ra hi-z hi-z *note2 *note1 *note3 t rfc mrs new command auto refresh new command
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 44/45 packing dimensions 54-lead tsop(ii) sdram (400mil) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 0.45 0.012 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c 0.12 0.21 0.005 0.008 c1 0.10 0.127 0.16 0.004 0.005 0.006 d 22.22 bsc 0.875 bsc zd 0.71 ref 0.028 ref e 11.76 bsc 0.463 bsc e1 10.16 bsc 0.400 bsc l 0.40 0.50 0.60 0.016 0.020 0.024 l1 0.80 ref 0.031 ref e 0.80 bsc 0.031 bsc r1 0.12 0.005 r2 0.12 0.25 0.005 0.010 0 8 0 8 1 0 0 2 10 15 20 10 15 20 3 10 15 20 10 15 20 y 0.100 0.004 see detail "a"
esmt M12L128168A elite semiconductor memory technology inc. publication date : sep. 2005 revision : 1.7 45/45 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critica l applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if pr oducts described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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